2012-11-25-0818Z


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Found by setting the CCR bit CLKSRC to 1, the 32768-Hz crystal is used and the seconds count increments reliably, even while the reset button is being pressed. Unfortunately, 1-second timing isn't good enough for any but the slowest Morse code and reading the CTC register isn't reliable when not using the system clock. So I found out the default divisor of CCLK is 4, which makes the 20MHz crystal give a 5MHz PCLK signal. Now to see if that clock works during reset, and if so, modify it to tick at maybe 20 times per second.

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last updated 2012-11-25 03:22:29. served from tektonic